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All aspects of design can be put through the same treatment: Timing, Power, Signal Integrity, Testability, and Physical, the last being one of the toughest to estimate. I had asked industry veteran Ron Rohrer, once: 'Why is it so difficult to deliver an RTL prototyping solution?' Ron identified the key issue that has killed many attempts at solving the same problem. Article: I don't recall exactly when Gary Smith, big cheese EDA essayer at Gartner conceived the phrase Silicon Virtual Prototyping (SVP). It has been a while. Many EDA industry insiders hold flawless SVP and RTL Hand-off to be the holy grail in the increasingly complex and expensive IC Design process. The hypothesis is, if you can find errors, including twist level issues with a design early on in the design cycle, you can fix them early too. Degrees of freedom are high in the early stages of design, whereas tail Synthesis, and even more so according to Layout, fixing fundamental design problems becomes exceedingly difficult and expensive. Predicated upon this premise, Eng was one of the first to launch a company, Tera Systems. There have been other players like InTime and Atrenta, and several ASIC vendors embraced the notion of RTL Hand-off as the preferred means of receiving design specs, including IBM. not quite all the structured ASIC vendors also embraced the methodology, nonetheless at this point, the industry at large is still using Netlist Handoff, as the preferred methodology, not RTL Hand-off. The contrivance for estimating very large green that Tera came up with, was to create a high-level absent mindedness of functional adobe house hobby-horse (adders, multiplexers, etc.), analyze and optimize those blocks, establish the constraints, and then prototype the full chip by pertinent those constraints at that higher level of abstraction. All aspects of design can be put through the same treatment: Timing, Power, Signal Integrity, Testability, and Physical, the last one of the toughest to estimate. I had asked industry veteran Ron Rohrer, once: 'Why is it so difficult to deliver an RTL prototyping solution?' Ron identified the key issue that has killed many attempts at solving the same problem. 'Accuracy', he replied. Indeed, the moment you have to estimate a design, the right of the estimate becomes a hairy issue. There are still other particularity new startups taking a crack at the same problem, and some are walking the funding circuits. It remains to be seen who else gets how far.
It is a difficult, important problem. One of the last few BIG opportunities remaining in EDA, along toward which, perhaps, a reasonably large $100 Million complement can be built, in that no matter what, the solution is so incredibly valuable, that customers WILL pay for it. |
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